PIC18F45K20-I/MV【PDF 89/234 页】MCU 32KB FLASH 1536B RAM 40-UQFN

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Sheet目录3873

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2007 Microchip Technology Inc.

Preliminary

DS70165E-page 177

dsPIC33F

15.1

PWM Time Base

The PWM time base is provided by a 15-bit timer with

a prescaler and postscaler. The time base is accessible

via the PTMR SFR. PTMR<15> is a read-only status

bit, PTDIR, that indicates the present count direction of

the PWM time base. If PTDIR is cleared, PTMR is

counting upwards. If PTDIR is set, PTMR is counting

downwards. The PWM time base is configured via the

PTCON SFR. The time base is enabled/disabled by

setting/clearing the PTEN bit in the PTCON SFR.

PTMR is not cleared when the PTEN bit is cleared in

software.

The PTPER SFR sets the counting period for PTMR.

The user must write a 15-bit value to PTPER<14:0>.

When the value in PTMR<14:0> matches the value in

PTPER<14:0>, the time base will either reset to ‘0’ or

reverse the count direction on the next occurring clock

cycle. The action taken depends on the operating

mode of the time base.

The PWM time base can be configured for four different

modes of operation:

Free-Running mode

Single-Shot mode

Continuous Up/Down Count mode

Continuous Up/Down Count mode with interrupts

for double updates

These four modes are selected by the PTMOD<1:0>

bits in the PTCON SFR. The Up/Down Count modes

support center-aligned PWM generation. The Single-

Shot mode allows the PWM module to support pulse

control of certain Electronically Commutative Motors

(ECMs).

The interrupt signals generated by the PWM time base

depend on the mode selection bits (PTMOD<1:0>) and

the postscaler bits (PTOPS<3:0>) in the PTCON SFR.

15.1.1

FREE-RUNNING MODE

In Free-Running mode, the PWM time base counts

upwards until the value in the PWM Time Base Period

reset on the following input clock edge, and the time

base will continue to count upwards as long as the

PTEN bit remains set.

When the PWM time base is in the Free-Running mode

(PTMOD<1:0> = 00), an interrupt event is generated

each time a match with the PTPER register occurs and

the PTMR register is reset to zero. The postscaler

selection bits may be used in this mode of the timer to

reduce the frequency of the interrupt events.

15.1.2

SINGLE-SHOT MODE

In Single-Shot mode, the PWM time base begins

counting upwards when the PTEN bit is set. When the

value in the PTMR register matches the PTPER regis-

ter, the PTMR register will be reset on the following

input clock edge, and the PTEN bit will be cleared by

the hardware to halt the time base.

When the PWM time base is in the Single-Shot mode

(PTMOD<1:0> = 01), an interrupt event is generated

when a match with the PTPER register occurs. The

PTMR register is reset to zero on the following input

clock edge and the PTEN bit is cleared. The postscaler

selection bits have no effect in this mode of the timer.

15.1.3

CONTINUOUS UP/DOWN COUNT

MODES

In the Continuous Up/Down Count modes, the PWM

time base counts upwards until the value in the PTPER

downwards on the following input clock edge. The

PTDIR bit in the PTMR SFR is read-only and indicates

the counting direction. The PTDIR bit is set when the

timer counts downwards.

In the Up/Down Count mode (PTMOD<1:0> = 10), an

interrupt event is generated each time the value of the

PTMR register becomes zero and the PWM time base

begins to count upwards. The postscaler selection bits

may be used in this mode of the timer to reduce the

frequency of the interrupt events.

Note:

If the PWM Period register is set to

0x0000, the timer will stop counting and

the interrupt and Special Event Trigger will

not be generated, even if the special event

value is also 0x0000. The module will not

update the PWM Period register if it is

already at 0x0000; therefore, the user

must disable the module in order to update

the PWM Period register.

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